In most video codec architectures, separate hardware or software on a processor implements the encoder core, and the frame memory is located outside of the encoder core. Generally, external memory implements the frame memory. As a result, an external bus transfers video data decoded in the local decoder loop inside the encoder core between the encoder core and the frame memory.
Transferring a large amount of data over the external bus between the encoder core and frame memory is costly. In the case of high definition video, using a frame resolution of 1448×1088 at thirty frames per second, the load on the external bus exceeds 400 megabytes per second. If the video compression utilizes bi-predictive pictures, the potential data transfer rate exceeds 800 megabytes per second.
Because of these high rates of data transfer, a large amount of costly frame memory is required to support the encoder. Additionally, the high data transfer rate across the external bus produces a great deal of heat and consumes a great deal of power.
Video encoding works best when reference memory segments pixel data into independent blocks allowing random access to the pixel data. Performance requirements determine the size of the block. One embodiment of the invention processes the luminance (Y) and chrominance (U and V) of each block differently according to different characteristics of the two components. The luminance is compressed mainly using prediction from neighboring pixels to reduce the dynamic range of the pixel data. The prediction requires preserving the value of first pixel in the compressed output. Otherwise, the prediction will generate some drift in other predicted pixel due to the inaccuracy of the reference value.